Symbols · WDT

Watchdog timer

Supervises a qualifying activity signal and operates its output when the documented watchdog timing condition is violated.

Schematic · WDTWatchdog timer: original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

Supervises a qualifying activity signal and operates its output when the documented watchdog timing condition is violated.

On a schematic, identify the watchdog input, enable and timeout configuration and trace the reset/fault output and supervised controller. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.

A watchdog supervises activity timing; it does not prove that the processor's control algorithm is correct.

The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.

How to read it

  • Identify the watchdog input, enable and timeout configuration.
  • Trace the reset/fault output and supervised controller.

Information to show or reference

  • Label the watchdog input, enable and timeout configuration.
  • Cross-reference the reset/fault output and supervised controller.
  • Add the selected device or circuit documentation revision, power/reference connections and project signal convention.

A distinction that matters

A watchdog supervises activity timing; it does not prove that the processor's control algorithm is correct.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

TPS3431 — watchdog timing supervision

Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.

Texas Instruments · Public reference checked 14 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 14 October 2026

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