SR-LATCH
Set-reset latch
Retains a digital state that is changed by the defined set or reset input conditions.
Schematic
IEEE / ANSI · SR
ANSI cross-coupled NOR latch
Two NOR gates cross-coupled to form an SR latch with active-high set and reset inputs.
In plain English
What does ANSI cross-coupled NOR latch mean?
Two NOR gates with each output fed back to an input of the other form an SR latch with active-high inputs. A high on set drives Q high, a high on reset drives Q low, and both low holds the state. Both high forces both outputs low and is normally treated as invalid.
A simple example
This form appears in educational schematics and in discrete logic designs where a spare quad NOR package provides a latch. It is the natural form when the set and reset signals are active-high commands.
What the drawings help you do
Like the NAND form, it shows construction rather than a guaranteed power-up state. A defined start-up condition needs extra circuitry or a reset pulse.
This particular reference
Two NOR gates cross-coupled to form an SR latch with active-high set and reset inputs. The cross-coupled NAND latch responds to active-low inputs.
- Signal
- Electrical information passed between devices, rather than necessarily the main power supply.
- Schematic
- A drawing showing function and connections rather than physical appearance.
Read the source: SN74HC02 — NOR gate logic
IEEE / ANSI · Two NOR outlines with each output fed back to the other gate's input
Distinctive-shape form as used in IEEE/ANSI-style schematics and manufacturer data books. Independent educational drawing; exact standard geometry and compliance are not asserted. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
Schematic · SR
What it represents
Two NOR gates with each output fed back to an input of the other form an SR latch with active-high inputs. A high on set drives Q high, a high on reset drives Q low, and both low holds the state. Both high forces both outputs low and is normally treated as invalid.
This form appears in educational schematics and in discrete logic designs where a spare quad NOR package provides a latch. It is the natural form when the set and reset signals are active-high commands.
Like the NAND form, it shows construction rather than a guaranteed power-up state. A defined start-up condition needs extra circuitry or a reset pulse.
How to read it
- Inputs are active high.
- Both inputs high gives both outputs low.
Information to show or reference
- Draw feedback paths clearly.
- Identify which output is Q.
- Show the power-up reset arrangement if needed.
A distinction that matters
The cross-coupled NAND latch responds to active-low inputs.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC02 — NOR gate logic
NOR gate documentation for the building block.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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