D-LATCH
Transparent D latch
Follows the input data while its latch-enable condition is active and retains it when that condition ends.
Schematic
Symbols · SR-LATCH
Set-reset latch
Retains a digital state that is changed by the defined set or reset input conditions.
Schematic · SR-LATCH
What it represents
Retains a digital state that is changed by the defined set or reset input conditions.
On a schematic, identify the set/reset active levels and any prohibited simultaneous condition and trace the stored output and reset/startup logic. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
Active-high and active-low SR implementations have different input conventions; a bare SR label does not resolve simultaneous-input behaviour.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the set/reset active levels and any prohibited simultaneous condition.
- Trace the stored output and reset/startup logic.
Information to show or reference
- Label the set/reset active levels and any prohibited simultaneous condition.
- Cross-reference the stored output and reset/startup logic.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
Active-high and active-low SR implementations have different input conventions; a bare SR label does not resolve simultaneous-input behaviour.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74LS279A — set-reset latches
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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