IEC · S R

IEC SR latch (rectangular form)

Rectangular IEC bistable with S and R inputs that set or reset the stored state immediately.

In plain English

What does IEC SR latch (rectangular form) mean?

The simplest IEC bistable is a rectangle with inputs labelled S and R and outputs Q and complemented Q. An active S sets the element to 1 and an active R resets it to 0, with no clock involved. Negation or polarity marks show active-low inputs, as on devices built from cross-coupled NAND gates.

A simple example

SR latches appear in alarm-latching and seal-in logic on control drawings. The key question for a reviewer is what happens when both S and R are active; dependency notation or a note should state whether set or reset dominates.

Identify the device and formRead the connections and stateCheck the equipment reference
A guide to reading this reference. The original symbol illustration and its drawing notes appear below; these boxes are not a wiring diagram.

What the drawings help you do

The symbol does not specify the power-up state. Where it matters, add the I=0 or I=1 additional drawing mark or a note. A separate reset or initialisation circuit is needed when the system requires a defined starting condition.

This particular reference

Rectangular IEC bistable with S and R inputs that set or reset the stored state immediately. A clocked SR flip-flop has 1S and 1R inputs under C1 control; the plain latch has none.

Normally open / normally closed
The contact state in the normal condition defined for the drawing.
Signal
Electrical information passed between devices, rather than necessarily the main power supply.
Schematic
A drawing showing function and connections rather than physical appearance.

Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74LS279A — set-reset latches

IEC · Rectangular bistable with S and R inputs

Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.

Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.

Schematic · S RIEC SR latch (rectangular form): original educational illustration
Original educational illustrationNot to scale · See source and graphic notes

What it represents

The simplest IEC bistable is a rectangle with inputs labelled S and R and outputs Q and complemented Q. An active S sets the element to 1 and an active R resets it to 0, with no clock involved. Negation or polarity marks show active-low inputs, as on devices built from cross-coupled NAND gates.

SR latches appear in alarm-latching and seal-in logic on control drawings. The key question for a reviewer is what happens when both S and R are active; dependency notation or a note should state whether set or reset dominates.

The symbol does not specify the power-up state. Where it matters, add the I=0 or I=1 qualifier or a note. A separate reset or initialisation circuit is needed when the system requires a defined starting condition.

How to read it

  • Check for active-low marks on S and R.
  • Look for a stated set or reset priority.

Information to show or reference

  • Label S and R inside the outline.
  • State the priority when both are active.
  • Specify the power-up state where relevant.

A distinction that matters

A clocked SR flip-flop has 1S and 1R inputs under C1 control; the plain latch has none.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A)

Usual meanings of S and R inputs and bistable symbols.

Texas Instruments · Public reference checked 28 October 2026 · Link only

SN74LS279A — set-reset latches

SR latch device documentation.

Texas Instruments · Public reference checked 14 October 2026 · Link only

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 28 October 2026

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