Set-reset latch
Retains a digital state that is changed by the defined set or reset input conditions.
Rectangular IEC bistable with S and R inputs that set or reset the stored state immediately.
In plain English
The simplest IEC bistable is a rectangle with inputs labelled S and R and outputs Q and complemented Q. An active S sets the element to 1 and an active R resets it to 0, with no clock involved. Negation or polarity marks show active-low inputs, as on devices built from cross-coupled NAND gates.
SR latches appear in alarm-latching and seal-in logic on control drawings. The key question for a reviewer is what happens when both S and R are active; dependency notation or a note should state whether set or reset dominates.
The symbol does not specify the power-up state. Where it matters, add the I=0 or I=1 additional drawing mark or a note. A separate reset or initialisation circuit is needed when the system requires a defined starting condition.
Rectangular IEC bistable with S and R inputs that set or reset the stored state immediately. A clocked SR flip-flop has 1S and 1R inputs under C1 control; the plain latch has none.
Read the source: Overview of IEEE Standard 91-1984: explanation of logic symbols (SDYZ001A) · SN74LS279A — set-reset latches
Qualifying-symbol and dependency conventions as explained in TI's public overview of IEEE Std 91-1984, which incorporates IEC 617-12 work. Independent educational drawing; not certified IEC geometry or an IEC database identifier. The counterpart is the matching functional concept; no equivalence of every detailed standard graphic is asserted.
Shown as an independently authored educational illustration. Use the cited publication and drawing legend to verify the required drafting form.
The simplest IEC bistable is a rectangle with inputs labelled S and R and outputs Q and complemented Q. An active S sets the element to 1 and an active R resets it to 0, with no clock involved. Negation or polarity marks show active-low inputs, as on devices built from cross-coupled NAND gates.
SR latches appear in alarm-latching and seal-in logic on control drawings. The key question for a reviewer is what happens when both S and R are active; dependency notation or a note should state whether set or reset dominates.
The symbol does not specify the power-up state. Where it matters, add the I=0 or I=1 qualifier or a note. A separate reset or initialisation circuit is needed when the system requires a defined starting condition.
A clocked SR flip-flop has 1S and 1R inputs under C1 control; the plain latch has none.
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
Usual meanings of S and R inputs and bistable symbols.
SR latch device documentation.
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
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