D-FF
Positive-edge D flip-flop
Captures its data input at the documented positive clock edge and retains that digital state.
Schematic
Symbols · D-LATCH
Transparent D latch
Follows the input data while its latch-enable condition is active and retains it when that condition ends.
Schematic · D-LATCH
What it represents
Follows the input data while its latch-enable condition is active and retains it when that condition ends.
On a schematic, identify the data input, latch-enable level and output-enable control and trace the retained data outputs and receiving circuit. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
A transparent latch is level-sensitive; a D flip-flop captures data at a defined clock transition.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the data input, latch-enable level and output-enable control.
- Trace the retained data outputs and receiving circuit.
Information to show or reference
- Label the data input, latch-enable level and output-enable control.
- Cross-reference the retained data outputs and receiving circuit.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
A transparent latch is level-sensitive; a D flip-flop captures data at a defined clock transition.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
SN74HC373 — transparent D latches
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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