D-FF
Positive-edge D flip-flop
Captures its data input at the documented positive clock edge and retains that digital state.
Schematic
Symbols · S/H
Sample-and-hold amplifier
Acquires an analogue signal during the documented sampling interval and retains a representation during hold.
Schematic · S/H
What it represents
Acquires an analogue signal during the documented sampling interval and retains a representation during hold.
On a schematic, identify the analogue input, sample/hold control and storage or timing reference and trace the held analogue output and converter interface. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.
Hold behaviour is an analogue acquisition function; it differs from digital storage in a latch or flip-flop.
The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.
How to read it
- Identify the analogue input, sample/hold control and storage or timing reference.
- Trace the held analogue output and converter interface.
Information to show or reference
- Label the analogue input, sample/hold control and storage or timing reference.
- Cross-reference the held analogue output and converter interface.
- Add the selected device or circuit documentation revision, power/reference connections and project signal convention.
A distinction that matters
Hold behaviour is an analogue acquisition function; it differs from digital storage in a latch or flip-flop.
Sources you can follow
These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.
AN-1515: sample-and-hold function using an analogue switch
Public primary manufacturer documentation establishes the component function or circuit/topology relationship. Preview geometry and drafting explanations are independently authored.
About this graphic
This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.
SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.
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