Serial-in parallel-out register

What it represents

Shifts serial input data through storage stages to parallel outputs at the documented clock events.

On a schematic, identify the serial input, shift clock and clear control and trace the parallel output bits and their bit-order mapping. Keep the component tag and signal/reference names consistent across the control drawing, terminal schedule and device documentation.

A SIPO register exposes its shifted bits; an output-latched register can retain a separate displayed output word.

The preview is an independently drawn educational functional reference. Add the selected component’s actual power pins, terminal numbers, timing or analogue reference details when producing a construction drawing.

How to read it

• Identify the serial input, shift clock and clear control.
• Trace the parallel output bits and their bit-order mapping.

Information to show or reference

• Label the serial input, shift clock and clear control.
• Cross-reference the parallel output bits and their bit-order mapping.
• Add the selected device or circuit documentation revision, power/reference connections and project signal convention.

Sources you can follow

These public references support the explanation and provide further detail. Their graphics and downloadable files remain with their publishers.

About this graphic

This illustration was authored independently by Elora Grid to explain the concept. It is not reproduced from a customer drawing, an official standard graphic or a manufacturer CAD file. Its correspondence to an exact IEC or IEEE symbol identifier has not been certified.

SVG and DXF downloads contain this original artwork. DXF uses unscaled drawing units; a GA envelope supplies no product dimensions, clearances or fabrication information. Original artwork is available under CC BY 4.0. Third-party references retain their own terms.

Entry JSON · Entry Markdown · Last editorial update: 14 October 2026