AND
AND gate
A logic element whose output is true when all stated positive-logic inputs are true.
Schematic
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Logic & signals
OR
OR gate
A positive-logic element whose output is true when at least one input is true.
Schematic
NAND
NAND gate
A logic gate that inverts the result of an AND operation.
Schematic
NOR
NOR gate
A logic gate that inverts an inclusive-OR result.
Schematic
XOR
Exclusive-OR gate
For two positive-logic inputs, produces a true output when the input states differ.
Schematic
XNOR
Exclusive-NOR gate
For two positive-logic inputs, produces a true output when the input states are equal.
Schematic
NOT
Logic inverter
Produces the opposite logical state of its defined digital input.
Schematic
BUF
Non-inverting logic buffer
Transfers a digital state through a non-inverting logic output stage.
Schematic
3STATE
Three-state logic buffer
A digital output stage that can drive logical states or enter its documented high-impedance state.
Schematic
SCHMITT-NOT
Schmitt-trigger inverter
A digital inverter with hysteresis between its input switching thresholds.
Schematic
SCHMITT
Schmitt-trigger buffer
A non-inverting digital element with separate rising and falling input thresholds.
Schematic
D-FF
Positive-edge D flip-flop
Captures its data input at the documented positive clock edge and retains that digital state.
Schematic
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