Logic & signals

Logic gates, signal processing and analogue functions used in control, automation and electronic diagrams. Explore 63 references, with original explanations and public primary sources.

AND

AND gate

A logic element whose output is true when all stated positive-logic inputs are true.

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OR

OR gate

A positive-logic element whose output is true when at least one input is true.

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NAND

NAND gate

A logic gate that inverts the result of an AND operation.

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NOR

NOR gate

A logic gate that inverts an inclusive-OR result.

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XOR

Exclusive-OR gate

For two positive-logic inputs, produces a true output when the input states differ.

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XNOR

Exclusive-NOR gate

For two positive-logic inputs, produces a true output when the input states are equal.

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NOT

Logic inverter

Produces the opposite logical state of its defined digital input.

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BUF

Non-inverting logic buffer

Transfers a digital state through a non-inverting logic output stage.

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3STATE

Three-state logic buffer

A digital output stage that can drive logical states or enter its documented high-impedance state.

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SCHMITT-NOT

Schmitt-trigger inverter

A digital inverter with hysteresis between its input switching thresholds.

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SCHMITT

Schmitt-trigger buffer

A non-inverting digital element with separate rising and falling input thresholds.

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D-FF

Positive-edge D flip-flop

Captures its data input at the documented positive clock edge and retains that digital state.

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JK-FF

Negative-edge JK flip-flop

Updates or toggles its stored state from J and K inputs at the selected negative clock edge.

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SR-LATCH

Set-reset latch

Retains a digital state that is changed by the defined set or reset input conditions.

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D-LATCH

Transparent D latch

Follows the input data while its latch-enable condition is active and retains it when that condition ends.

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SIPO

Serial-in parallel-out register

Shifts serial input data through storage stages to parallel outputs at the documented clock events.

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PISO

Parallel-in serial-out register

Loads a parallel word and presents its bits through a serial shift output.

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SHIFT-LATCH

Shift register with output latch

Combines a serial shift path with a separate output-storage stage.

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CTR-RIP

Ripple binary counter

Counts clock events through cascaded storage stages whose output changes do not occur simultaneously.

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CTR-SYNC

Synchronous binary counter

Updates its binary count from a common clock with the documented count-enable, load and clear controls.

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DECADE

Decoded decade counter

Advances a decoded output sequence through the documented ten-state counter arrangement.

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ONE-SHOT

Retriggerable monostable

Produces a timed output pulse that can be extended by a qualifying retrigger condition.

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DEC

Binary decoder / demultiplexer

Uses binary selection and enable conditions to activate the documented selected output.

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ENC-PRI

Priority encoder

Encodes the highest-priority qualifying input into the specified binary output word.

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MUX

Digital multiplexer

Selects one of several digital inputs for the documented output according to its selection controls.

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MAG-COMP

Digital magnitude comparator

Compares two digital words to provide the specified equality and magnitude indications.

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ADD

Binary full adder

Adds binary input words with the documented carry-in and produces sum and carry outputs.

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BUS-TR

Logic bus transceiver

Drives data between two digital buses according to the selected direction and enable conditions.

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LEVEL

Logic voltage-level translator

Transfers digital information between the documented logic-voltage domains.

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OC-BUF

Open-collector buffer

Provides a logic output through a transistor pull-down stage requiring the documented external load or pull-up.

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PARITY

Parity generator / checker

Computes a parity indication from the defined digital input word.

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PLL

Phase-locked loop

Controls an oscillator through a phase-comparison feedback arrangement to follow the documented reference.

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VCO

Voltage-controlled oscillator

Generates an oscillating output whose frequency responds to the documented control voltage.

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CLK-GEN

Clock generator

Provides the documented clock signal or signals used by digital circuitry.

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WDT

Watchdog timer

Supervises a qualifying activity signal and operates its output when the documented watchdog timing condition is violated.

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OP-AMP

Operational amplifier

An analogue amplifier represented by inverting and non-inverting inputs, an output and its supply connections.

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COMP

Voltage comparator

Compares two analogue input voltages and produces the documented output-state indication.

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INA

Instrumentation amplifier

Amplifies a differential input signal using an instrumentation-amplifier input and gain arrangement.

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DIFF-AMP

Difference amplifier

Produces an analogue output related to the difference between two input signals with the documented gain/reference arrangement.

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FDA

Fully differential amplifier

Processes an analogue input to provide two complementary output signals around a defined common-mode level.

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CSA

Current-sense amplifier

Amplifies a voltage associated with a current-sensing shunt using the selected measurement-input arrangement.

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ISO-AMP

Isolation amplifier

Transfers an analogue measurement across the documented electrical isolation boundary.

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OTA

Operational transconductance amplifier

Produces an output current controlled by its differential input voltage and documented bias arrangement.

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MULT

Analogue multiplier

Produces an analogue output related to the product of two input quantities and the selected scaling/summing arrangement.

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A-SW

Analogue bilateral switch

Connects or disconnects an analogue signal path under its documented digital control.

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A-MUX

Analogue multiplexer

Selects a continuous-signal channel through the documented controlled switching arrangement.

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S/H

Sample-and-hold amplifier

Acquires an analogue signal during the documented sampling interval and retains a representation during hold.

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ADC

Analogue-to-digital converter

Converts a sampled analogue quantity into the selected digital representation.

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DAC

Digital-to-analogue converter

Converts a digital code into the documented analogue output quantity.

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VREF-S

Series voltage reference

Provides a reference voltage through a series-connected supply and output arrangement.

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VREF-H

Shunt voltage reference

Establishes a reference voltage using a shunt-current path and the documented bias or feedback circuit.

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PREC-RECT

Precision rectifier

Uses an active amplifier/diode arrangement to rectify a signal according to the documented circuit.

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RMS-DC

RMS-to-DC converter

Produces a DC output related to the RMS value of its input signal under the selected implementation.

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V/F

Voltage / frequency converter

Converts between an analogue voltage and a pulse-frequency representation in the documented selected configuration.

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INV-AMP

Inverting amplifier circuit

Uses an amplifier feedback connection that produces the documented inverted signal relationship.

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NI-AMP

Non-inverting amplifier circuit

Uses an amplifier feedback arrangement to amplify a signal without the intended polarity inversion.

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INTEGRATOR

Op-amp integrator

Uses a documented amplifier/capacitor feedback arrangement to obtain an integrating signal response.

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DIFFERENTIATOR

Op-amp differentiator

Uses an amplifier input/feedback arrangement to obtain a differentiating response over its intended operating band.

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LPF

Active low-pass filter

Passes the intended lower-frequency signal content while attenuating higher-frequency content through an active filter circuit.

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HPF

Active high-pass filter

Attenuates lower-frequency content while passing the intended higher-frequency signal band.

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BPF

Active band-pass filter

Passes an intended frequency band while attenuating content below and above that band.

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NOTCH

Active notch filter

Attenuates a defined frequency region while retaining the intended content outside it.

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TIA

Transimpedance amplifier

Converts an input current into an output voltage through the documented feedback arrangement.

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